Digital delay generator

ABSTRACT

Circuitry for generating a virtually jitter free delay relative to a start pulse and for generating such delays over both integer and non-integer multiples of the time interval between timing pulses. The circuitry includes delay circuitry and signal generating circuitry. The delay circuitry is responsive to the start pulse and to the timing pulses for generating first and second signal edges. The second signal edge occurs later in time than the first signal edge, and both signal edges occur following the start pulse and in timed relation to the timing pulses. The signal generating circuitry is connected to the delay circuitry and has an output for generating an output signal which includes a timing cycle of known duration. The signal generating circuitry is responsive to the start pulse for initiating the timing cycle, the first signal edge for interrupting the timing cycle, and the second signal edge for reinitiating the timing cycle. The output signal begins in timed relation to the start pulse and terminates in timed relation to the end of the timing cycle following interruption.

The Government has rights in this invention pursuant to Contract No.DAAB07-77-C-2187 awarded by the Department of the Army.

CROSS REFERENCES TO RELATED APPLICATIONS

Reference should be made to my copending application entitled"Interruptable Signal Generator" which is filed on even date herewithand which is assigned to the same assignee as the present application.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to non-synchronous clocked digital delaygenerator systems and, more particularly, to generating virtually jitterfree delays relative to a start pulse and for generating such delaysover both integer and non-integer multiples of the time interval betweenclocked timing pulses.

2. Description of the Prior Art

A typical prior art digital delay generator system generates a delayrelative to a start pulse which is unsynchronized to timing pulsescounted by the system. Because the start pulse is unsynchronized to thetiming pulses, a period of time up to the time interval between timingpulses can occur between receipt of the start pulse and detection by thedelay generator system of the first subsequent timing pulse. Thisuncertainty in time between the occurrence of the start pulse and thefirst counted timing pulse is commonly referred to as jitter.Accordingly, because the start pulse can occur at any time betweenadjacent timing pulses, and because the counter will only count at aspecific point in the cycle between timing pulses, typically at theleading edge of each timing pulse, a jitter of up to the time intervalbetween adjacent timing pulses will exist in the time delay establishedby the system.

Another disadvantage of typical digital delay generator systems is that,without supplementary circuitry, the nominal delays available arelimited to integer multiples of the time interval between timing pulses.Therefore, nominal delays ending between timing pulses cannot beselected.

SUMMARY OF THE INVENTION

The present invention is a digital delay generator system for generatingvirtually jitter free delays relative to a start pulse and forgenerating such delays over both integer and non-integer multiples ofthe time interval between timing pulses.

The system includes delay apparatus responsive to the start pulse andthe timing pulses for generating first and second signal edges, thesecond signal edge occurring later in time than the first signal edge,both signal edges occurring following the start pulse and in timedrelation to the timing pulses.

The system also includes signal generating apparatus connected to thedelay apparatus. The signal generating apparatus has an output forgenerating an output signal which includes a timing cycle of knownduration. The signal generating apparatus is responsive to the startpulse for initiating the timing cycle, the first signal edge forinterrupting the timing cycle and the second signal edge forreinitiating the timing cycle. The output signal begins in timedrelation to the start pulse and terminates in timed relation to the endof the timing cycle following interruption.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating the preferred embodiment of the presentinvention.

FIG. 2 illustrates signals appearing at various points in the circuit ofFIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT Structure

Referring now more particularly to FIG. 1 and to the details of thepresent invention, the network can be seen to include an input terminal12, a count enable flip-flop 13, a crystal oscillator clock 14, a delaycounter 15, an interrupt enable flip-flop 32, a one-shot multivibrator("one-shot") 33, a capacitor 34, two diodes 36 and 37, a variableresistor 35, a supply voltage terminal 43, a pulse generator 16, and anoutput terminal 17.

Input terminal 12 is connected to input 18 of count enable flip-flop 13and to input 38 of one-shot 33.

The output of count enable flip-flop 13 is connected to an input 19 ofdelay counter 15. The output of crystal oscillator clock 14 is connectedto an input 20 of delay counter 15.

Two outputs 39 and 41 of delay counter 15 are connected to two inputs 40and 42, respectively, of interrupt enable flip-flop 32.

The output of interrupt enable flip-flop 32 and a first timing input ofone-shot 33 are connected through diodes 36 and 37 which are connectedand oriented for forward current flow away from each other. Capacitor 34is connected between the first timing input of one-shot 33 and a secondtiming input of one-shot 33. Capacitor charging current is derived fromsupply voltage terminal 43 which is connected through variable resistor35 to a junction between diodes 36 and 37.

In the configuration shown in FIG. 1, the output of one-shot 33 isconnected to the input of pulse generator 16, and the output of pulsegenerator 16 is connected to output terminal 17 as well as to a resetinput 22 of count enable flip-flop 13 and to a reset input 23 of delaycounter 15. In an alternate configuration, pulse generator 16 can beeliminated, and the output of one-shot 33 can be connected directly tooutput terminal 17 as well as to input 22 of count enable flip-flop 13and to input 23 of delay counter 15. In this alternate configuration,count enable flip-flop 13 and delay counter 15 must be of the type thatwill reset on a specific signal edge (transition) rather than on asignal level.

Count enable flip-flop 13 and interrupt enable flip-flop 32 can becomprised of an SN5474, which is a dual integrated circuit; one-shot 33and pulse generator 16 can comprise an SN54123, which is also a dualintegrated circuit; and delay counter 15 can comprise at least oneSN54197. These integrated circuits may be found in any TTL data book.

Operation

Referring now to the signals illustrated in FIG. 2, the operation of thepresent invention will be described.

Non-synchronous start pulse A is received at terminal 12 and at input 18of count enable flip-flop 13. Start pulse A toggles count enableflip-flop 13 which then enables delay counter 15 to begin counting thetiming pulses as soon thereafter as they are received from crystaloscillator clock 14 which is continuously running.

Following receipt at terminal 12, start pulse A is transmitted not onlyto input 18 of count enable flip-flop 13 but also to input 38 ofone-shot 33. One-shot 33 then begins generating an output signal with atiming cycle having a duration predetermined primarily by the values ofcapacitor 34 and variable resistor 35.

If one-shot 33 were not interrupted, the timing cycle would continuewithout interruption over the time it takes for the charging current tocharge capacitor 34 to a predetermined threshold at which time theoutput signal of one-shot 33 would terminate. Accordingly, at time t_(o)when start pulse A is received at input 38 of one-shot 33, the one-shotoutput signal begins (see signal D) as the potential across capacitor 34begins to rise (see signal E).

On a specific early count from delay counter 15 (the beginning of thesecond timing pulse at t₂ on clock wave train B is optimum) an interruptenable command comprising at least a first signal edge is received fromoutput 39 of delay counter 15 (e.g., from the Q_(A) output of anSN54197) by input 40 of interrupt enable flip-flop 32, causing theinterrupt enable flip-flop output signal to go from high to low as shownat time t₂ in signal F. This low output signal at the output ofinterrupt enable flip-flop 32 then shunts the one-shot charging currentfrom supply voltage terminal 43 through variable resistor 35 and diode36 into the output of interrupt enable flip-flop 32 through a transistorleg to ground.

With the capacitor charging current thus shunted, one-shot 33 iseffectively in a "memory" mode since no charge or discharge path existsfor capacitor 34 (diode 36 prevents any charging of capacitor 34 by thenormal output of interrupt enable flip-flop 32, and diode 37 preventsany discharge of capacitor 34). Thus, one-shot 33 will not continue itstiming cycle until interrupt enable flip-flop 32 is reset as disccusedfurther below.

Although the means including diodes 36 and 37 could have beenconstructed in a wide variety of ways, including through the use oftransistors, the use of diodes was selected.

On a predetermined later timing pulse corresponding to a desired delay,a clocked reset signal comprising at least a second signal edge isreceived from output 41 of delay counter 15 by input 42 of interruptenable flip-flop 32. Receipt of the reset signal causes interrupt enablefip-flop 32 to be reset and its output to return high as shown at timet_(b) in signal F.

With interrupt enable flip-flop 32 in its reset state, the high outputsignal precludes further shunting of the capacitor charging current toground. Thus, capacitor 34 once again begins charging (see signal E attime t_(b)), and one-shot 33 resumes the remaining portion of its timingcycle. The remaining portion will be its normal full cycle time less theamount of time that occurred between start pulse A at time t_(o) and theclocked interrupt enable command at time t₂.

The timing cycle of one-shot 33 ends when the charge on capacitor 34reaches a predetermined threshold. At this time, as illustrated at timet_(j) in FIG. 2, capacitor 34 discharges (see signal E) and the one-shot33 output signal terminates (see Signal D).

Time t_(j) at the trailing edge of signal D is a virtually jitter freetime, precisely delayed from time t_(o) at the leading edges of inputstart pulse A and signal D. As desired and as shown by the apparatusillustrated in FIG. 1, the trailing edge of output signal D may be usedto trigger generation of a delayed signal G by way of pulse generator16. Signal G is made available through output terminal 17. In addition,as desired, delayed signal G can also be routed to input 22 of countenable flip-flop 13 and to input 23 of delay counter 15 for the purposeof resetting these devices. With this arrangement, which is alsoillustrated in FIG. 1, count enable flip-flop 13 and delay counter 15are reset in response to delayed signal G.

In the alternative, as was previously described, pulse generator 16 canbe eliminated, and the output of one-shot 33 can be connected directlyto output terminal 17. In this manner, the trailing edge of signal D isused directly for timing purposes. In addition, as desired, the outputof one-shot 33 can be connected directly to input 22 of count enableflip-flop 13 and to input 23 of delay counter 15 such that these deviceswill be reset in response to the trailing edge of signal D.

The time between t_(o) and t_(j) is equal to the one-shot 33 cycle timeplus the time determined by the integer multiple of the timing pulseswhich occur during the time that one-shot 33 is in its "memory" mode.Accordingly, as shown in FIG. 2, the total delay time between time t_(o)and t_(j) is the total of time periods T_(INITIAL), T_(MEMORY), andT_(FINAL).

T_(INITIAL) is the first portion of the one-shot 33 timing cycle. Itoccurs between time t_(o) at the leading edge of start pulse A and timet₂ when the interrupt enable command toggles interrupt enable flip-flop32, thus causing the one-shot 33 timing cycle to be interrupted.

T_(MEMORY) is the time period during which the one-shot 33 timing cycleis effectively in a "memory" mode. It is the time period between time t₂when the one-shot 33 timing cycle is interrupted and time t_(b) when theclocked reset signal resets interrupt enable flip-flop 32, thusrecommencing the charging of capacitor 34 and the timing of the one-shot33 timing cycle. T_(MEMORY) is equal to an exact multiple of the timeinterval between adjacent timing pulses since both the interrupt enablecommand and the reset signal are clocked, occurring at the leading edgesof timing pulses.

T_(FINAL) is the final or remaining portion of the one-shot 33 timingcycle and is equal to the normal one-shot 33 cycle time less the amountof time that occurs during T_(INITIAL). It occurs between time t_(b)when the reset signal resets interrupt enable flip-flop 32, thus causingthe one-shot 33 timing cycle to resume, and time t_(j) when one-shot 33reaches the end of its timing cycle.

The selection of times t₂ and t_(b) is, of course, arbitrary and can bevaried according to design considerations and applications. A primaryconcern is to have the time period between times t_(o) and t₂ and thetime period between times t_(b) and t_(j) long enough so that anytransients arising at times t_(o) and t_(b) will have suitablystabilized by times t₂ and t_(j), respectively.

The frequency of crystal oscillator clock 14 can also, of course, varyaccording to application. In two different applications of the presentinvention, a 10 megahertz clock (each clock period having 100nanoseconds) and a 20 megahertz clock (each clock period having 50nanoseconds) have been used.

The normal full timing cycle of one-shot 33 (T_(INITIAL) plus T_(FINAL))can vary from as short a time as two clock periods to as long a time asone might desire. Timing cycles as long as microseconds have beenexperimented with. In two different applications of the presentinvention, timing cycles were nominally 350 nanoseconds and wereadjustable by approximately one clock period. (In the embodiment shownin FIG. 1, the timing cycle of one-shot 33 is made adjustable throughthe use of variable resistor 35. Note that, in addition to or in thealternative to using a variable resistor 35 to adjust the timing cycle avariable capacitor could be used in lieu of capacitor 34.)

By having the timing cycle of one-shot 33 adjustable, the total timedelay between t_(o) and t_(j) is not only virtually jitter free but issusceptible to precise refinement as well. It may be desired, forexample, to have a total time delay equal to an integer multiple of thetime interval between timing pulses. Such a result can be achieved bysetting the timing cycle of one-shot 33 equal to an integer multiple ofthe clock period, e.g., 350 nanoseconds for a 20 megahertz clock havinga 50 nanosecond clock period. In such a case, the total delay will be350 nanoseconds (T_(INITIAL) plus T_(FINAL)) plus T_(MEMORY), which isdetermined by the integer multiple of clock periods of delay which occurduring the time that one-shot 33 is in its "memory" mode.

On the other hand, total delay times other than integer multiples of theclock period may be desired. If in a system with a 100 megahertz clockhaving a 100 nanosecond clock period one desired a total delay of aninteger multiple of clock periods plus 40 nanoseconds, one could set thetiming cycle of one-shot 33 (T_(INITIAL) plus T_(FINAL)) to, forexample, 340 nanoseconds. The total time delay would then be equal to340 nanoseconds (T_(INITIAL) plus T_(FINAL)) plus whatever T_(MEMORY)integer multiple of 100 nanosecond clock periods are selected.

T_(MEMORY), the time during which one-shot 33 is interrupted and held inits "memory" mode, can be as long as desired. In two applications of thepresent invention, T_(MEMORY) was approximately 52 microseconds.

In the preceding discussion, times have generally been referred to asoccurring at particular times such as t₀, t₂, t_(b), and t_(j). Inreality, of course, there is virtually always some inherent delay withinthe components of a system as well as over signal rise times. If allsuch delays are equal or are known, the resulting uncertainty, ifsignificant, can be accounted for. In addition, of course, one caninsert known delays in timed relation to times such as those mentionedabove and still have an equivalent system since the effect of suchdelays can be accounted for.

The embodiments of the invention in which an exclusive property or rightis claimed are defined as follows:
 1. A digital delay generator forgenerating a virtually jitter free delay relative to a start pulse andfor generating such a delay over any practicable multiple of the timeinterval between timing pulses, such multiple including a non-integer,comprising:delay means responsive to the start pulse and to the timingpulses for generating first and second signal edges, the second signaledge occurring later in time than the first signal edge, both signaledges occurring following the start pulse and in timed relation to thetiming pulses; and signal generating means connected to the delay meansand having an output for generating an output signal which includes atiming cycle of a fixed known duration, the signal generating means.[.being.]. .Iadd.comprising means .Iaddend.responsive to .Iadd.(1).Iaddend.the start pulse for initiating the timing cycle .Iadd.in timedrelation to the start pulse.Iaddend., .Iadd.(2) .Iaddend.the firstsignal edge for interrupting the timing cycle .[.for an indefiniteperiod.]. .Iadd.to initiate a hold thereon.Iaddend., and .Iadd.(3).Iaddend.the second signal edge for reestablishing the timing cycle andpermitting the timing cycle to continue, .[.the output signal.]..Iadd.the signal generating means further comprising means for.Iaddend.beginning .Iadd.the output signal .Iaddend.in timed relation tothe .[.start pulse.]. .Iadd.beginning of the timing cycle .Iaddend.and.Iadd.for .Iaddend.terminating .Iadd.the output signal .Iaddend.in timedrelation to the end of the timing cycle following interruption, so thata virtually jitter free delay with respect to the start pulse isgenerated.
 2. Apparatus according to claim 1 wherein the signalgenerating means further comprises:first means for initiating the timingcycle in timed relation to the start pulse and for providing the outputsignal, the first means being connected to receive the start pulse and;second means for interrupting the timing cycle in timed relation to thefirst signal edge and for reinitiating the timing cycle in timedrelation to the second signal edge, the second means being connected tothe delay means and to the first means.
 3. Apparatus according to claim2 wherein the first means comprises a one-shot multivibrator having aninput for receiving the start pulse and an output for providing theoutput signal, the one-shot multivibrator also having a timing capacitorconnected between a first timing input and a second timing input. 4.Apparatus according to claim 3 wherein the second means comprises aninterrupt enable flip-flop having an output connected to a third meansfor selectively permitting the charging of the capacitor, the thirdmeans being connected to the capacitor, and wherein the interrupt enableflip-flop is connected to receive the first and second signal edges, theinterrupt enable flip-flop output having a normal first signal levelending in response to the first signal edge and recommencing in responseto the second signal edge, and having a second signal level between theending and recommencing of the first signal level, the charging of thecapacitor occurring following the start pulse while the first signallevel is present until the capacitor charge reaches a known level, thetiming cycle ending in timed relation to the time that the capacitorreaches the known charge level.
 5. Apparatus according to claim 4wherein the third means includes a resistor through which the capacitoris charged.
 6. Apparatus according to claim 5 wherein the third meansfurther comprises two diodes connected for current flow away from eachother, the diodes being connected betweeen the interrupt enableflip-flop output and the timing capacitor and wherein one end of theresistor is connected to a junction between the two diodes, the otherend of the resistor being connected to a terminal adapted to receive asupply voltage.
 7. Apparatus according to claim 6 further comprisingtiming pulse supply means for providing the timing pulses, the timingpulse supply means being connected to the delay means.
 8. Apparatusaccording to claim 7 further comprising enable means for enabling thedelay means to be responsive to the start pulse, the enable means beingconnected to receive the start pulse and connected to the delay means.9. Apparatus according to claim 8 wherein the delay means comprises adelay counter having a first input connected to an output of the enablemeans, a second input connected to receive the timing pulses, a firstoutput for providing the first signal edge, and a second output forproviding the second signal edge.
 10. Apparatus according to claim 9wherein the interrupt enable flip-flop further comprises a first inputconnected to receive the first signal edge and a second input connectedto receive the second signal edge.
 11. Apparatus according to claim 10wherein the enable means and the delay counter further comprise resetmeans for resetting the enable means and the delay counter, the resetmeans being connected to the one-shot multivibrator output through anoutput means, the output means being connected to an output terminal.12. Apparatus according to claim 11 wherein the output means comprisespulse generating means having an output for providing a delayed signalin response to the termination of the output signal, the pulsegenerating means output being connected to the reset means and to theoutput terminal.
 13. Apparatus according to claim 1 further comprisingtiming pulse supply means for providing the timing pulses, the timingpulse supply means being connected to the delay means.
 14. Apparatusaccording to claim 13 further comprising enable means for enabling thedelay means to be responsive to the start pulse, the enable means beingconnected to receive the start pulse and connected to the delay means.15. Apparatus according to claim 14 wherein the delay means comprises adelay counter having a first input connected to an output of the enablemeans, a second input connected to receive the timing pulses, a firstoutput for providing the first signal edge, and a second output forproviding the second signal edge.
 16. Apparatus according to claim 2further comprising timing pulse supply means for providing the timingpulses, the timing pulse supply means being connected to the delaymeans.
 17. Apparatus according to claim 16 further comprising enablemeans for enabling the delay means to be responsive to the start pulse,the enable means being connected to receive the start pulse andconnected to the delay means.
 18. Apparatus according to claim 17wherein the delay means comprises a delay counter having a first inputconnected to an output of the enable means, a second input connected toreceive the timing pulses, a first output for providing the first signaledge, and a second output for providing the second signal edge.
 19. Amethod for generating a virtually jitter free delay relative to a startpulse and for generating such a delay over any practicable multiple ofthe time interval between timing pulses, such multiple including anon-integer, comprising:generating first and second signal edges intimed relation to timing pulses, the second signal edge occurring laterin time than the first signal edge, both signal edges occurringfollowing the start pulse; generating a signal in response to the startpulse, the signal including a timing cycle of a .[.fix.]. .Iadd.fixed.Iaddend.known duration, the .[.signal.]. .Iadd.timing cycle.Iaddend.beginning in timed relation to the start pulse; interruptingthe timing cycle .[.for an indefinite period.]..Iadd.to initiate a holdthereon.Iaddend., the interruption .[.being.]. .Iadd.beginning.Iaddend.in response to the first signal edge; reestablishing the timingcycle in response to the second signal edge, thus permitting the timingcycle to continue, the signal .Iadd.beginning in timed relation to thebeginning of the timing cycle .Iaddend.terminating in timed relation tothe end of the timing cycle following interruption, so that a virtuallyjitter free delay with respect to the start pulse is generated.